`timescale 1ps / 1ps
module Registers(input clk,
                 input [1:0] RegWr,
                 input [4:0] Ra,
                 input [4:0] Rb,
                 input [4:0] Rw,
                 input [31:0] busW,
                 input R31wr,
                 input [31:2] Bnpc,
                 output [31:0] busA,
                 output [31:0] busB
                );
    
    reg [31:0] rf [31:0];
    
    initial begin
        rf[0] = 0;
    end
    
    always @(posedge clk) begin
        if (RegWr != 0) rf[Rw] <= busW;
        if (R31wr) rf[31] <= Bnpc;
    end
    
    assign busA = (Ra != 0)? rf[Ra]:0;
    assign busB = (Rb != 0)? rf[Rb]:0;
    
endmodule
